With the recent increased communication traffic, there has been a demand for a transmission apparatus achieving data communications with higher speed, larger capacity, and higher quality. To meet such demand, some transmission apparatus employs a high-speed serial memory as a memory to temporarily hold received data within the transmission apparatus. This high-speed serial memory is provided as a packet buffer in a reception unit of the transmission apparatus, for example, and is used as a memory from which data is read within a certain period of time after the data is written, even though the read order of the data changes according to the priority.
There is one using a serializer/deserializer (Serdes) transceiver as an interface of the high-speed serial memory. In the Serdes, an error occurs probabilistically (with a predetermined probability) due to noise or the like on a transmission path within the transmission apparatus. When the Serdes has an access error (write error) to the high-speed serial memory, a retry (another write processing) to the high-speed serial memory within the transmission apparatus is performed in order to reduce data loss and to ensure data quality.
Moreover, there is a technique for data transmission between apparatuses to reduce a retry frequency, by monitoring a state of a reception buffer in a reception-side apparatus, obtaining a reference time corresponding to the time of occurrence of a retry request, and controlling data read from a transmission buffer in a transmission-side apparatus.
Japanese Laid-open Patent Publication No. 2010-191569 is known as an example of prior art.
In the above prior technique, a data transmission amount between the apparatuses may not be reduced since data is transmitted between the apparatuses upon every retry.
Moreover, when the Serdes is used as a memory interface in the transmission apparatus, a retry to the serial memory is performed in the transmission apparatus upon occurrence of a write error to the high-speed serial memory. Therefore, an access band of the high-speed serial memory is occupied. When an interface speed of the Serdes is increased in response to the band occupancy, power consumption is significantly increased.